邓仰东

邓仰东，男，清华大学副教授。卡内基·梅隆大学电子与计算机工程系博士（2006年） 。现任教于清华大学软件工程学院，担任清华大学微电子学研究所副研究员、 NVIDIA合作教授。曾获清华大学邓锋基金、清华大学挑战杯优秀指导教师奖、清华大学骨干人才基金。

2006年，获得卡内基·梅隆大学(Carnegie Mellon University)电子与计算机工程系博士学位。

1998年，获得清华大学电子工程系工学硕士学位。

1995年，获得清华大学电子工程系工学学士学位。

2004年5月– 2006年3月，高级软件工程师Incentia Design Automation。

2006年3月 – 2008年3月，软件架构师Magma Design Automation(Synopsys)。

2008年3月–今，副研究员清华大学微电子学研究所。

2010年 –今,NVIDIA合作教授。

2012年,VLSI Design Journal特邀主编Jan.

2009年—2013年,Technical program committeeIEEE Computer Society Annual Symposium onVLSI.

2013年,HPC China.

2012年,ASP-DAC.

2010年,ACM International Workshop on Timing Issues in the Specification andSynthesis of Digital Systems.

2010年,IEEE/ACM Great Lakes Symposium on VLSI.

2009年—2013年CUDA校园编程竞赛评委。

高性能计算机体系结构, 电子设计自动化和嵌入式系统。

2012至今，轨道车辆嵌入式网络通信设备硬件子课题清华大学与北车集团联合科研项目。

2012年–2016年，基于光线追踪机制的三维集成图形处理器体系结构研究中国国家自然科学基金。

2012年–2015年，三维集成光线追踪图形处理器体系结构研究清华大学自主科研计划。

2012年-2013年，基于现代图形处理器的超大规模并行逻辑仿真Intel国际合作。

2010年-2011年，基于仿真的开源片上平台建模环境Intel国际合作。

2009年-2010年，基于仿真的开源片上平台建模环境Intel国际合作。

2013年度国际计算机设计会议(International Conference on Computer Design）最佳论文奖。

2009年，获得NVIDIA合作教授奖。

2010年，获得清华大学挑战杯优秀指导教师奖。

2008年，获得清华大学骨干人才基金。

2008年，获得清华大学邓锋基金。

2006年，获得NEC项目技术成就奖, Magma Design Automation。

专著

1.Y. Deng, X. Xie, and S. Wei，“Designing ARM based System-on-Chip”, Elsevier Publishing Company, 即将出版.

2.Y. Deng, H. Chen, and Y. Liu, “Parallel Programming for Many-Core Processors,” Higher Education Publishing House, 2014.

3.Y. Deng and W. Maly, “3-D VLSI – A 2.5-D Integration Scheme,” Springer Verlag/Tsinghua University Publishing House, 2010.

4.Z. Wang and Y. Deng, “Structural VLSI Design and High Level Synthesis,” Tsinghua Publishing House, 1998. (清华大学集成电路设计课程教材)

1.Y.DengandS. Mu, “A Survey on GPU Based Electronic Design Automation Computing,” Invited Paper, Foundation and Trends in Electronics Design Automation, Now Publishers, 2013, (单行本综述论文，180页).

2.Y. Deng, D. Wang, and Y. Zhu, “Asynchronous Parallel Logic Simulation on Modern Graphics Processors,” Why Scientists and Engineers Need GPUs, Springer, 2012.

3.Y. Deng, “Hardware/Software Co-Design for System-on-Chips,” Communications of China Computer Federation, Feb. 2012.

4.Y. Deng, "GPU Accelerated VLSI Design Verification," Invited paper, First International Workshop on Frontier of GPU Computing, Jun. 2010.

1.T. Wang and Y. Deng, “Mining Effective Parallelism from Hidden Coherence for GPU Based Path Tracing,” SIGGRAPH Asia, 2013.

2.K. Fang, Y. Ni, J. He, Z. Li, S. Mu, and Y. Deng, “FastLane: An FPGA Accelerated GPU Microarchitecture Simulator,” IEEE International Conference on Computer Design, 2013. (最佳论文奖)

3.H. Qian and Y. Deng, “Accelerating RTL Simulation with GPUs,” IEEE/ACM International Conference on Computer-Aided Design, Nov. 2011.

4.Y. Zhu, Y. Deng, and Y. Chen, “Hermes: An Integrated CPU/GPU Microarchitecture for IP Routing,” Design Automation Conference, 2011.

5.S. Mu, C. Wang, M. Liu, D. Li, M. Zhu, X. Chen, X. Xie, and Y. Deng, “Evaluating the Potential of Graphics Processors for High Performance Embedded Computing,” Design Automation and Test Europe, 2011.

6.K. Kang, and Y. Deng, “Scalable Packet Classification via GPU Meta-programming,” Design Automation and Test Europe, Apr. 2011.

7.J. Zhao, X. Zhang, X. Wang, Y. Deng, and X. Fu, “Exploiting Graphics Processors for High-performance IP Lookup in Software Routers,” INFOCOM, 2011.

8.B. Wang, Y. Zhu, and Y. Deng, “Distributed Time, Conservative Parallel Logic Simulation on GPUs,” Design Automation Conference, Jun. 2010.

9.J. Xue, X. Jiao, Y. Deng, H. Qian, D. Zeng, G. Li, and Z. Yu, "Massively Parallel Finite Element Simulator for Full-Chip STI Stress Analysis," First International Workshop on Frontier of GPU Computing, Jun. 2010.

10.S. Mu, J. Lu, N. Zhang, X. Zhang, Y. Deng, and S. Zhang, “IP Routing Processing with GraphicProcessors,” Design Automation and Test Europe, Apr. 2010.

11.Y. Deng, B. Wang, and S. Mu, “Taming Irregular EDA Applications on GPUs,” IEEE/ACM International Conference on Computer-Aided Design, Nov. 2009.

12.J. Xue, L. Yang, Y. Deng, Z. Ye, and Z. Yu, "Layout-Dependent STI Stress Analysis and Stress-Aware RF/Analog Circuit Design Optimization," IEEE/ACM International Conference on Computer-Aided Design, Nov. 2009.

1.S. Mu, Y. Deng, et. al. “Orchestrating Cache Management and Memory Scheduling for GPGPU Applications”, IEEE Transaction on Very Large Scale Integration, accepted.

2.S. Mu, Y. Deng, et. al. “Exploiting the Task-Pipelined Parallelism of Stream Programs on Many-Core GPUs” IEICE Transaction on Information and System, accepted.

3.H. Qian, Y. Deng, B. Wang, and S. Mu, “Towards Accelerating Irregular EDA Applications with GPUs,” Integration, the VLSI Journal, 2012.

4.J. Xue, Y. Deng, Z. Ye,et al. “A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit Optimization,” IEEE Transaction on Very Large Scale Integration, Mar. 2012.

5.G. Sun, S. Xu, X. Wang, D. Wang, E. Tang. Y. Deng, and S. Chen, “A High-Throughput, High-Accuracy System-Level Simulation Framework for System-on-Chips,” VLSI Design Journal, Jan. 2012.

6.Y. Zhu, B. Wang, and Y. Deng, “Massively Parallel Logic Simulation with GPUs,” ACM Transaction on Design Automation of Electronics Systems, Vol.16, No.3, June, 2011.

7.X. Chen, Y. Deng, X. Chen, X. Li, and J. Tian, “GPU Based High Speed FIR Digital Filtering,” Journal on Computer Aided Design and Graphics, Sep. 2010.

8.J. Xue, T. Li, Y. Deng, and Z. Yu, “Full-Chip Leakage Verification for 65nm CMOS Node and Beyond,” Integration, the VLSI Journal, Sep., 2010.

9.Y. Deng and P. Li, “Temperature-Aware Floorplanning of 3-D ICs Considering Thermal Dependent Leakage Power,” Journal of Low Power Electronics, Aug. 2006.

10.Y. Deng and W. Maly, “2.5-Dimensional VLSI System Integration,” IEEE Transaction on Very Large Scale Integration, Aug., 2005   .